/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Sent_Reg.h                                                                                *
 *  \brief    This file contains interface header for Sent low level driver.                            *
 *            register description file.                                                                *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2024/10/22     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/
#ifndef SENT_REG_H
#define SENT_REG_H

/********************************************************************************************************
 *                                 Private Macro definition                                             *
 *******************************************************************************************************/
#define REVISION_OFF  0x0U

#define FM_REVISION_INTR_STAT  ((uint32_t)0xffU << 18U)
#define FV_REVISION_INTR_STAT(v) \
  (((uint32_t)(v) << 18U) & FM_REVISION_INTR_STAT)
#define GFV_REVISION_INTR_STAT(v) \
  (((uint32_t)(v) & FM_REVISION_INTR_STAT) >> 18U)

#define BM_REVISION_GLOBAL_CLOCK_GATING  ((uint32_t)0x01U << 17U)

#define BM_REVISION_GLOBAL_SW_RESET  ((uint32_t)0x01U << 16U)

#define CHANNEL_RESET_OFF  0x4U

#define BM_CHANNEL_RESET_DEBUG_LOW_POWER  ((uint32_t)0x01U << 27U)

#define BM_CHANNEL_RESET_QSTAT_MASK_INT  ((uint32_t)0x01U << 26U)

#define BM_CHANNEL_RESET_QSTAT_WAIT_INT  ((uint32_t)0x01U << 25U)

#define FM_CHANNEL_RESET_CHANNEL_CLK_EN  ((uint32_t)0xffU << 16U)
#define FV_CHANNEL_RESET_CHANNEL_CLK_EN(v) \
  (((uint32_t)(v) << 16U) & FM_CHANNEL_RESET_CHANNEL_CLK_EN)
#define GFV_CHANNEL_RESET_CHANNEL_CLK_EN(v) \
  (((uint32_t)(v) & FM_CHANNEL_RESET_CHANNEL_CLK_EN) >> 16U)

#define FM_CHANNEL_RESET_CHANNEL_EN  ((uint32_t)0xffU << 8U)
#define FV_CHANNEL_RESET_CHANNEL_EN(v) \
  (((uint32_t)(v) << 8U) & FM_CHANNEL_RESET_CHANNEL_EN)
#define GFV_CHANNEL_RESET_CHANNEL_EN(v) \
  (((uint32_t)(v) & FM_CHANNEL_RESET_CHANNEL_EN) >> 8U)

#define FM_CHANNEL_RESET_CHANNEL_SW_RST ((uint32_t)0xffU << 0UL)
#define FV_CHANNEL_RESET_CHANNEL_SW_RST(v) \
  (((uint32_t)(v) << 0U) & FM_CHANNEL_RESET_CHANNEL_SW_RST)

#define BM_CHANNEL_RESET_CHANNEL7_SW_RST  ((uint32_t)0x01U << 7U)

#define BM_CHANNEL_RESET_CHANNEL6_SW_RST  ((uint32_t)0x01U << 6U)

#define BM_CHANNEL_RESET_CHANNEL5_SW_RST  ((uint32_t)0x01U << 5U)

#define BM_CHANNEL_RESET_CHANNEL4_SW_RST  ((uint32_t)0x01U << 4U)

#define BM_CHANNEL_RESET_CHANNEL3_SW_RST  ((uint32_t)0x01U << 3U)

#define BM_CHANNEL_RESET_CHANNEL2_SW_RST  ((uint32_t)0x01U << 2U)

#define BM_CHANNEL_RESET_CHANNEL1_SW_RST  ((uint32_t)0x01U << 1U)

#define BM_CHANNEL_RESET_CHANNEL0_SW_RST  ((uint32_t)0x01U << 0U)

#define CHANNEL_PRE_DIVIDER_OFF(n)  (0x8U + 4U*(n))

#define FM_CHANNEL_PRE_DIVIDER_TICK_COUNTER  ((uint32_t)0x3fffU << 8U)
#define FV_CHANNEL_PRE_DIVIDER_TICK_COUNTER(v) \
  (((uint32_t)(v) << 8U) & FM_CHANNEL_PRE_DIVIDER_TICK_COUNTER)
#define GFV_CHANNEL_PRE_DIVIDER_TICK_COUNTER(v) \
  (((uint32_t)(v) & FM_CHANNEL_PRE_DIVIDER_TICK_COUNTER) >> 8U)

#define FM_CHANNEL_PRE_DIVIDER_FRACTIONAL_PRE_DIV  ((uint32_t)0xffU << 0U)
#define FV_CHANNEL_PRE_DIVIDER_FRACTIONAL_PRE_DIV(v) \
  (((uint32_t)(v) << 0U) & FM_CHANNEL_PRE_DIVIDER_FRACTIONAL_PRE_DIV)
#define GFV_CHANNEL_PRE_DIVIDER_FRACTIONAL_PRE_DIV(v) \
  (((uint32_t)(v) & FM_CHANNEL_PRE_DIVIDER_FRACTIONAL_PRE_DIV) >> 0U)

#define CHANNEL_CTRL_OFF(n)  (0x28U + 4U*(n))

#define FM_CHANNEL_CTRL_CHN_WDT_LEN  ((uint32_t)0xffffU << 16U)
#define FV_CHANNEL_CTRL_CHN_WDT_LEN(v) \
  (((uint32_t)(v) << 16U) & FM_CHANNEL_CTRL_CHN_WDT_LEN)
#define GFV_CHANNEL_CTRL_CHN_WDT_LEN(v) \
  (((uint32_t)(v) & FM_CHANNEL_CTRL_CHN_WDT_LEN) >> 16U)

#define BM_CHANNEL_CTRL_WDT_EN  ((uint32_t)0x01U << 15U)

#define BM_CHANNEL_CTRL_WDT_CLR  ((uint32_t)0x01U << 14U)

#define BM_CHANNEL_CTRL_IDLE_TIMEOUT  ((uint32_t)0x01U << 13U)

#define BM_CHANNEL_CTRL_SER_FIRST_IGNORE  ((uint32_t)0x01U << 12U)

#define BM_CHANNEL_CTRL_CRC4_ACE  ((uint32_t)0x01U << 11U)

#define BM_CHANNEL_CTRL_NIB_CNT_MODE  ((uint32_t)0x01U << 10U)

#define BM_CHANNEL_CTRL_CALIB_PULSE_VAR  ((uint32_t)0x01U << 9U)

#define BM_CHANNEL_CTRL_STATUS_NIB_CRC  ((uint32_t)0x01U << 8U)

#define BM_CHANNEL_CTRL_NIBBBLE_CRC_EN  ((uint32_t)0x01U << 7U)

#define BM_CHANNEL_CTRL_SER_CRC_EN  ((uint32_t)0x01U << 6U)

#define BM_CHANNEL_CTRL_PULSE_CHK_OFF  ((uint32_t)0x01U << 5U)

#define BM_CHANNEL_CTRL_PULSE_DET_MODE  ((uint32_t)0x01U << 4U)

#define BM_CHANNEL_CTRL_NIBBLE_SAMPLE_MODE  ((uint32_t)0x01U << 3U)

#define BM_CHANNEL_CTRL_INI_PULSE_SUSCCHK  ((uint32_t)0x01U << 2U)

#define BM_CHANNEL_CTRL_CRC4_SER_MODE  ((uint32_t)0x01U << 1U)

#define BM_CHANNEL_CTRL_CRC4_MODE  ((uint32_t)0x01U << 0U)

#define CHANNEL_STATUS_OFF(n)  (0x48U + 4U*(n))

#define CHANNEL_STATUS_VALID_BIT (0xf01fffffUL)

#define BM_CHANNEL_STATUS_NIB_FRAME_READY  ((uint32_t)0x01U << 31U)

#define BM_CHANNEL_STATUS_SER_FRAME_READY  ((uint32_t)0x01U << 30U)

#define BM_CHANNEL_STATUS_SPC_IDLE  ((uint32_t)0x01U << 29U)

#define BM_CHANNEL_STATUS_TX_IDLE  ((uint32_t)0x01U << 28U)

#define BM_CHANNEL_STATUS_PULSE_CNT_OFLOW  ((uint32_t)0x01U << 20U)

#define BM_CHANNEL_STATUS_NIB_FRAME_UNDER_RUN  ((uint32_t)0x01U << 19U)

#define BM_CHANNEL_STATUS_SER_FRAME_UNDER_RUN  ((uint32_t)0x01U << 18U)

#define BM_CHANNEL_STATUS_SPC_UNEXP_TRIG  ((uint32_t)0x01U << 17U)

#define BM_CHANNEL_STATUS_SPC_UNEXP_PLS  ((uint32_t)0x01U << 16U)

#define BM_CHANNEL_STATUS_CAL_LEN_20_ERR  ((uint32_t)0x01U << 15U)

#define BM_CHANNEL_STATUS_SUS_FRAME_LEN_ERR  ((uint32_t)0x01U << 14U)

#define BM_CHANNEL_STATUS_CALIB_PUSLE_LOW  ((uint32_t)0x01U << 13U)

#define BM_CHANNEL_STATUS_NIBBLE_PUSLE_LOW  ((uint32_t)0x01U << 12U)

#define BM_CHANNEL_STATUS_FALL_GLITCH_FLAG  ((uint32_t)0x01U << 11U)

#define BM_CHANNEL_STATUS_RISE_GLITCH_FLAG  ((uint32_t)0x01U << 10U)

#define BM_CHANNEL_STATUS_DATA_CRC_ERR  ((uint32_t)0x01U << 9U)

#define BM_CHANNEL_STATUS_SER_MSG_CRC_ERR  ((uint32_t)0x01U << 8U)

#define BM_CHANNEL_STATUS_NUM_EDGE_ERR  ((uint32_t)0x01U << 7U)

#define BM_CHANNEL_STATUS_NIBBLE_VAL_ERR  ((uint32_t)0x01U << 6U)

#define BM_CHANNEL_STATUS_CAL_DRIFT_ERR  ((uint32_t)0x01U << 5U)

#define BM_CHANNEL_STATUS_DATA_OFLOW  ((uint32_t)0x01U << 4U)

#define BM_CHANNEL_STATUS_SER_MSG_OFLOW  ((uint32_t)0x01U << 3U)

#define BM_CHANNEL_STATUS_CAL_LEN_ERR  ((uint32_t)0x01U << 2U)

#define BM_CHANNEL_STATUS_CAL_RESYNC  ((uint32_t)0x01U << 1U)

#define BM_CHANNEL_STATUS_BUS_IDLE  ((uint32_t)0x01U << 0U)

#define CHN_FRAME_CTRL_OFF(n)  (0x68U + 4U*(n))

#define BM_CHN_FRAME_CTRL_FRAME_INVA_IGNORE  ((uint32_t)0x01U << 11U)

#define BM_CHN_FRAME_CTRL_SER_ENH_EN  ((uint32_t)0x01U << 10U)

#define BM_CHN_FRAME_CTRL_FRAME_LEN_CHK  ((uint32_t)0x01U << 9U)

#define BM_CHN_FRAME_CTRL_CHN_PAUSE  ((uint32_t)0x01U << 8U)

#define FM_CHN_FRAME_CTRL_CHN_FRAME_NIB  ((uint32_t)0x7U << 0U)
#define FV_CHN_FRAME_CTRL_CHN_FRAME_NIB(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_FRAME_CTRL_CHN_FRAME_NIB)
#define GFV_CHN_FRAME_CTRL_CHN_FRAME_NIB(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_CTRL_CHN_FRAME_NIB) >> 0U)

#define CHN_FRAME_NIB_P_OFF(n)  (0x88U + 4U*(n))
#define CHN_FRAME_NIB_P_RESERVED (0x88888888UL)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER7  ((uint32_t)0x7U << 28U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER7(v) \
  (((uint32_t)(v) << 28U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER7)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER7(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER7) >> 28U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER6  ((uint32_t)0x7U << 24U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER6(v) \
  (((uint32_t)(v) << 24U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER6)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER6(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER6) >> 24U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER5  ((uint32_t)0x7U << 20U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER5(v) \
  (((uint32_t)(v) << 20U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER5)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER5(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER5) >> 20U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER4  ((uint32_t)0x7U << 16U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER4(v) \
  (((uint32_t)(v) << 16U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER4)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER4(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER4) >> 16U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER3  ((uint32_t)0x7U << 12U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER3(v) \
  (((uint32_t)(v) << 12U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER3)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER3(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER3) >> 12U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER2  ((uint32_t)0x7U << 8U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER2(v) \
  (((uint32_t)(v) << 8U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER2)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER2(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER2) >> 8U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER1  ((uint32_t)0x7U << 4U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER1(v) \
  (((uint32_t)(v) << 4U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER1)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER1(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER1) >> 4U)

#define FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER0  ((uint32_t)0x7U << 0U)
#define FV_CHN_FRAME_NIB_P_RCV_NIB_POINTER0(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER0)
#define GFV_CHN_FRAME_NIB_P_RCV_NIB_POINTER0(v) \
  (((uint32_t)(v) & FM_CHN_FRAME_NIB_P_RCV_NIB_POINTER0) >> 0U)

#define INPUT_FILTER_CTRL_OFF(n)  (0x108U + 4U*(n))

#define BM_INPUT_FILTER_CTRL_CHN_IN_INV  ((uint32_t)0x01U << 31U)

#define BM_INPUT_FILTER_CTRL_CHN_OUT_INV  ((uint32_t)0x01U << 30U)

#define BM_INPUT_FILTER_CTRL_CHN_ALT_INPUT  ((uint32_t)0x01U << 29U)

#define BM_INPUT_FILTER_CTRL_CHN_IGNORE_INI_GLITCH  ((uint32_t)0x01U << 16U)

#define BM_INPUT_FILTER_CTRL_CHN_F_GLITCH_CLR  ((uint32_t)0x01U << 15U)

#define BM_INPUT_FILTER_CTRL_CHN_R_GLITCH_CLR  ((uint32_t)0x01U << 14U)

#define FM_INPUT_FILTER_CTRL_CHN_F_DEPTH  ((uint32_t)0x3fU << 8U)
#define FV_INPUT_FILTER_CTRL_CHN_F_DEPTH(v) \
  (((uint32_t)(v) << 8U) & FM_INPUT_FILTER_CTRL_CHN_F_DEPTH)
#define GFV_INPUT_FILTER_CTRL_CHN_F_DEPTH(v) \
  (((uint32_t)(v) & FM_INPUT_FILTER_CTRL_CHN_F_DEPTH) >> 8U)

#define FM_INPUT_FILTER_CTRL_CHN_R_DEPTH  ((uint32_t)0x3fU << 0U)
#define FV_INPUT_FILTER_CTRL_CHN_R_DEPTH(v) \
  (((uint32_t)(v) << 0U) & FM_INPUT_FILTER_CTRL_CHN_R_DEPTH)
#define GFV_INPUT_FILTER_CTRL_CHN_R_DEPTH(v) \
  (((uint32_t)(v) & FM_INPUT_FILTER_CTRL_CHN_R_DEPTH) >> 0U)

#define TIME_STAMP_CONTROL_OFF  0x130U

#define BM_TIME_STAMP_CONTROL_TIMER_RESET  ((uint32_t)0x01U << 31U)

#define BM_TIME_STAMP_CONTROL_TIMER_START  ((uint32_t)0x01U << 30U)

#define BM_TIME_STAMP_CONTROL_TIMER_CNT_LATCH_MODE  ((uint32_t)0x01U << 29U)

#define BM_TIME_STAMP_CONTROL_TIMER_CNT_LATCH_EN  ((uint32_t)0x01U << 28U)

#define FM_TIME_STAMP_CONTROL_TIMER_DIV  ((uint32_t)0xffffffU << 0U)
#define FV_TIME_STAMP_CONTROL_TIMER_DIV(v) \
  (((uint32_t)(v) << 0U) & FM_TIME_STAMP_CONTROL_TIMER_DIV)
#define GFV_TIME_STAMP_CONTROL_TIMER_DIV(v) \
  (((uint32_t)(v) & FM_TIME_STAMP_CONTROL_TIMER_DIV) >> 0U)

#define TIME_STAMP_COUNTER_OFF  0x134U

#define FM_TIME_STAMP_COUNTER_TIMER_COUNTER  ((uint32_t)0xffffffffU << 0U)
#define FV_TIME_STAMP_COUNTER_TIMER_COUNTER(v) \
  (((uint32_t)(v) << 0U) & FM_TIME_STAMP_COUNTER_TIMER_COUNTER)
#define GFV_TIME_STAMP_COUNTER_TIMER_COUNTER(v) \
  (((uint32_t)(v) & FM_TIME_STAMP_COUNTER_TIMER_COUNTER) >> 0U)

#define DMA_CTRL_OFF  0x140U

#define FM_DMA_CTRL_CHN_DMA_NIB_EN_MASK  ((uint32_t)0xffU << 24U)
#define FV_DMA_CTRL_CHN_DMA_NIB_EN_MASK(v) \
  (((uint32_t)(v) << 24U) & FM_DMA_CTRL_CHN_DMA_NIB_EN_MASK)
#define GFV_DMA_CTRL_CHN_DMA_NIB_EN_MASK(v) \
  (((uint32_t)(v) & FM_DMA_CTRL_CHN_DMA_NIB_EN_MASK) >> 24U)

#define FM_DMA_CTRL_CHN_DMA_SER_EN_MASK  ((uint32_t)0xffU << 16U)
#define FV_DMA_CTRL_CHN_DMA_SER_EN_MASK(v) \
  (((uint32_t)(v) << 16U) & FM_DMA_CTRL_CHN_DMA_SER_EN_MASK)
#define GFV_DMA_CTRL_CHN_DMA_SER_EN_MASK(v) \
  (((uint32_t)(v) & FM_DMA_CTRL_CHN_DMA_SER_EN_MASK) >> 16U)

#define BM_DMA_CTRL_DMA_FIFO_SRST  ((uint32_t)0x01U << 1U)

#define BM_DMA_CTRL_DMA_START  ((uint32_t)0x01U << 0U)

#define FUSA_REG_OFF  0x160U

#define BM_FUSA_REG_DEBUGMODE_EN  ((uint32_t)0x01U << 27U)

#define FM_FUSA_REG_PWECCINJ  ((uint32_t)0x7fU << 20U)
#define FV_FUSA_REG_PWECCINJ(v) \
  (((uint32_t)(v) << 20U) & FM_FUSA_REG_PWECCINJ)
#define GFV_FUSA_REG_PWECCINJ(v) \
  (((uint32_t)(v) & FM_FUSA_REG_PWECCINJ) >> 20U)

#define FM_FUSA_REG_DMAFWCODEINJ  ((uint32_t)0xfU << 16U)
#define FV_FUSA_REG_DMAFWCODEINJ(v) \
  (((uint32_t)(v) << 16U) & FM_FUSA_REG_DMAFWCODEINJ)
#define GFV_FUSA_REG_DMAFWCODEINJ(v) \
  (((uint32_t)(v) & FM_FUSA_REG_DMAFWCODEINJ) >> 16U)

#define FM_FUSA_REG_DMAFWDATAINJ  ((uint32_t)0xfU << 12U)
#define FV_FUSA_REG_DMAFWDATAINJ(v) \
  (((uint32_t)(v) << 12U) & FM_FUSA_REG_DMAFWDATAINJ)
#define GFV_FUSA_REG_DMAFWDATAINJ(v) \
  (((uint32_t)(v) & FM_FUSA_REG_DMAFWDATAINJ) >> 12U)

#define FM_FUSA_REG_DMABWCODEINJ  ((uint32_t)0xfU << 8U)
#define FV_FUSA_REG_DMABWCODEINJ(v) \
  (((uint32_t)(v) << 8U) & FM_FUSA_REG_DMABWCODEINJ)
#define GFV_FUSA_REG_DMABWCODEINJ(v) \
  (((uint32_t)(v) & FM_FUSA_REG_DMABWCODEINJ) >> 8U)

#define FM_FUSA_REG_DMABWDATAINJ  ((uint32_t)0xfU << 4U)
#define FV_FUSA_REG_DMABWDATAINJ(v) \
  (((uint32_t)(v) << 4U) & FM_FUSA_REG_DMABWDATAINJ)
#define GFV_FUSA_REG_DMABWDATAINJ(v) \
  (((uint32_t)(v) & FM_FUSA_REG_DMABWDATAINJ) >> 4U)

#define BM_FUSA_REG_ERRINJINTRUNCORR  ((uint32_t)0x01U << 3U)

#define BM_FUSA_REG_ERRINJINTRCORR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_REG_ERRINJINTR  ((uint32_t)0x01U << 1U)

#define BM_FUSA_REG_SELFTESTMODE_EN  ((uint32_t)0x01U << 0U)

#define FUSA_APB_OFF  0x164U

#define FM_FUSA_APB_PWDATAINJ  ((uint32_t)0xffffffffU << 0U)
#define FV_FUSA_APB_PWDATAINJ(v) \
  (((uint32_t)(v) << 0U) & FM_FUSA_APB_PWDATAINJ)
#define GFV_FUSA_APB_PWDATAINJ(v) \
  (((uint32_t)(v) & FM_FUSA_APB_PWDATAINJ) >> 0U)

#define PRDATAINJ_OFF  0x168U

#define REG_PARITY_ERR_INT_STAT_OFF  0x16cU

#define BM_REG_PARITY_ERR_INT_STAT_B0  ((uint32_t)0x01U << 0U)

#define REG_PARITY_ERR_INT_STAT_EN_OFF  0x170U

#define BM_REG_PARITY_ERR_INT_STAT_EN_B0  ((uint32_t)0x01U << 0U)

#define REG_PARITY_ERR_INT_SIG_EN_OFF  0x174U

#define BM_REG_PARITY_ERR_INT_SIG_EN_B0  ((uint32_t)0x01U << 0U)

#define CHANNEL_STA_OFF(n)  (0x180U + 12U*(n))

#define CHANNEL_STA_VALID_BIT (0xc01fffffUL)

#define BM_CHANNEL_STA_NIB_FRAME_READY  ((uint32_t)0x01U << 31U)

#define BM_CHANNEL_STA_SER_FRAME_READY  ((uint32_t)0x01U << 30U)

#define BM_CHANNEL_STA_PULSE_CNT_OFLOW  ((uint32_t)0x01U << 20U)

#define BM_CHANNEL_STA_NIB_FRAME_UNDER_RUN  ((uint32_t)0x01U << 19U)

#define BM_CHANNEL_STA_SER_FRAME_UNDER_RUN  ((uint32_t)0x01U << 18U)

#define BM_CHANNEL_STA_SPC_UNEXP_TRIG  ((uint32_t)0x01U << 17U)

#define BM_CHANNEL_STA_SPC_UNEXP_PLS  ((uint32_t)0x01U << 16U)

#define BM_CHANNEL_STA_CAL_LEN_20_ERR  ((uint32_t)0x01U << 15U)

#define BM_CHANNEL_STA_SUS_FRAME_LEN_ERR  ((uint32_t)0x01U << 14U)

#define BM_CHANNEL_STA_CALIB_PUSLE_LOW  ((uint32_t)0x01U << 13U)

#define BM_CHANNEL_STA_NIBBLE_PUSLE_LOW  ((uint32_t)0x01U << 12U)

#define BM_CHANNEL_STA_FALL_GLITCH_FLAG  ((uint32_t)0x01U << 11U)

#define BM_CHANNEL_STA_RISE_GLITCH_FLAG  ((uint32_t)0x01U << 10U)

#define BM_CHANNEL_STA_DATA_CRC_ERR  ((uint32_t)0x01U << 9U)

#define BM_CHANNEL_STA_SER_MSG_CRC_ERR  ((uint32_t)0x01U << 8U)

#define BM_CHANNEL_STA_NUM_EDGE_ERR  ((uint32_t)0x01U << 7U)

#define BM_CHANNEL_STA_NIBBLE_VAL_ERR  ((uint32_t)0x01U << 6U)

#define BM_CHANNEL_STA_CAL_DRIFT_ERR  ((uint32_t)0x01U << 5U)

#define BM_CHANNEL_STA_DATA_OFLOW  ((uint32_t)0x01U << 4U)

#define BM_CHANNEL_STA_SER_MSG_OFLOW  ((uint32_t)0x01U << 3U)

#define BM_CHANNEL_STA_CAL_LEN_ERR  ((uint32_t)0x01U << 2U)

#define BM_CHANNEL_STA_CAL_RESYNC  ((uint32_t)0x01U << 1U)

#define BM_CHANNEL_STA_BUS_IDLE  ((uint32_t)0x01U << 0U)

#define CHANNEL_STA_EN_OFF(n)  (0x184U + 12U*(n))

#define BM_CHANNEL_STA_EN_NIB_FRAME_READY  ((uint32_t)0x01U << 31U)

#define BM_CHANNEL_STA_EN_SER_FRAME_READY  ((uint32_t)0x01U << 30U)

#define BM_CHANNEL_STA_EN_PULSE_CNT_OFLOW  ((uint32_t)0x01U << 20U)

#define BM_CHANNEL_STA_EN_NIB_FRAME_UNDER_RUN  ((uint32_t)0x01U << 19U)

#define BM_CHANNEL_STA_EN_SER_FRAME_UNDER_RUN  ((uint32_t)0x01U << 18U)

#define BM_CHANNEL_STA_EN_SPC_UNEXP_TRIG  ((uint32_t)0x01U << 17U)

#define BM_CHANNEL_STA_EN_SPC_UNEXP_PLS  ((uint32_t)0x01U << 16U)

#define BM_CHANNEL_STA_EN_CAL_LEN_20_ERR  ((uint32_t)0x01U << 15U)

#define BM_CHANNEL_STA_EN_SUS_FRAME_LEN_ERR  ((uint32_t)0x01U << 14U)

#define BM_CHANNEL_STA_EN_CALIB_PUSLE_LOW  ((uint32_t)0x01U << 13U)

#define BM_CHANNEL_STA_EN_NIBBLE_PUSLE_LOW  ((uint32_t)0x01U << 12U)

#define BM_CHANNEL_STA_EN_FALL_GLITCH_FLAG  ((uint32_t)0x01U << 11U)

#define BM_CHANNEL_STA_EN_RISE_GLITCH_FLAG  ((uint32_t)0x01U << 10U)

#define BM_CHANNEL_STA_EN_DATA_CRC_ERR  ((uint32_t)0x01U << 9U)

#define BM_CHANNEL_STA_EN_SER_MSG_CRC_ERR  ((uint32_t)0x01U << 8U)

#define BM_CHANNEL_STA_EN_NUM_EDGE_ERR  ((uint32_t)0x01U << 7U)

#define BM_CHANNEL_STA_EN_NIBBLE_VAL_ERR  ((uint32_t)0x01U << 6U)

#define BM_CHANNEL_STA_EN_CAL_DRIFT_ERR  ((uint32_t)0x01U << 5U)

#define BM_CHANNEL_STA_EN_DATA_OFLOW  ((uint32_t)0x01U << 4U)

#define BM_CHANNEL_STA_EN_SER_MSG_OFLOW  ((uint32_t)0x01U << 3U)

#define BM_CHANNEL_STA_EN_CAL_LEN_ERR  ((uint32_t)0x01U << 2U)

#define BM_CHANNEL_STA_EN_CAL_RESYNC  ((uint32_t)0x01U << 1U)

#define BM_CHANNEL_STA_EN_BUS_IDLE  ((uint32_t)0x01U << 0U)

#define CHANNEL_SIG_EN_OFF(n)  (0x188U + 12U*(n))

#define BM_CHANNEL_SIG_EN_NIB_FRAME_READY  ((uint32_t)0x01U << 31U)

#define BM_CHANNEL_SIG_EN_SER_FRAME_READY  ((uint32_t)0x01U << 30U)

#define BM_CHANNEL_SIG_EN_PULSE_CNT_OFLOW  ((uint32_t)0x01U << 20U)

#define BM_CHANNEL_SIG_EN_NIB_FRAME_UNDER_RUN  ((uint32_t)0x01U << 19U)

#define BM_CHANNEL_SIG_EN_SER_FRAME_UNDER_RUN  ((uint32_t)0x01U << 18U)

#define BM_CHANNEL_SIG_EN_SPC_UNEXP_TRIG  ((uint32_t)0x01U << 17U)

#define BM_CHANNEL_SIG_EN_SPC_UNEXP_PLS  ((uint32_t)0x01U << 16U)

#define BM_CHANNEL_SIG_EN_CAL_LEN_20_ERR  ((uint32_t)0x01U << 15U)

#define BM_CHANNEL_SIG_EN_SUS_FRAME_LEN_ERR  ((uint32_t)0x01U << 14U)

#define BM_CHANNEL_SIG_EN_CALIB_PUSLE_LOW  ((uint32_t)0x01U << 13U)

#define BM_CHANNEL_SIG_EN_NIBBLE_PUSLE_LOW  ((uint32_t)0x01U << 12U)

#define BM_CHANNEL_SIG_EN_FALL_GLITCH_FLAG  ((uint32_t)0x01U << 11U)

#define BM_CHANNEL_SIG_EN_RISE_GLITCH_FLAG  ((uint32_t)0x01U << 10U)

#define BM_CHANNEL_SIG_EN_DATA_CRC_ERR  ((uint32_t)0x01U << 9U)

#define BM_CHANNEL_SIG_EN_SER_MSG_CRC_ERR  ((uint32_t)0x01U << 8U)

#define BM_CHANNEL_SIG_EN_NUM_EDGE_ERR  ((uint32_t)0x01U << 7U)

#define BM_CHANNEL_SIG_EN_NIBBLE_VAL_ERR  ((uint32_t)0x01U << 6U)

#define BM_CHANNEL_SIG_EN_CAL_DRIFT_ERR  ((uint32_t)0x01U << 5U)

#define BM_CHANNEL_SIG_EN_DATA_OFLOW  ((uint32_t)0x01U << 4U)

#define BM_CHANNEL_SIG_EN_SER_MSG_OFLOW  ((uint32_t)0x01U << 3U)

#define BM_CHANNEL_SIG_EN_CAL_LEN_ERR  ((uint32_t)0x01U << 2U)

#define BM_CHANNEL_SIG_EN_CAL_RESYNC  ((uint32_t)0x01U << 1U)

#define BM_CHANNEL_SIG_EN_BUS_IDLE  ((uint32_t)0x01U << 0U)

#define FUSA_INT_STA_OFF  0x1f0U

#define BM_FUSA_INT_STA_DEBUGMODEERR  ((uint32_t)0x01U << 15U)

#define BM_FUSA_INT_STA_PCTL1UNCORRERR  ((uint32_t)0x01U << 13U)

#define BM_FUSA_INT_STA_PCTL0UNCORRERR  ((uint32_t)0x01U << 12U)

#define BM_FUSA_INT_STA_PUSERUNCORRERR  ((uint32_t)0x01U << 11U)

#define BM_FUSA_INT_STA_PADDRUNCORRERR  ((uint32_t)0x01U << 10U)

#define BM_FUSA_INT_STA_PWDATAUNCORRERR  ((uint32_t)0x01U << 9U)

#define BM_FUSA_INT_STA_PWDATACORRERR  ((uint32_t)0x01U << 8U)

#define BM_FUSA_INT_STA_PWDATAFATALERR  ((uint32_t)0x01U << 7U)

#define BM_FUSA_INT_STA_DMAUNCORRERR  ((uint32_t)0x01U << 6U)

#define BM_FUSA_INT_STA_DMACORRERR  ((uint32_t)0x01U << 5U)

#define BM_FUSA_INT_STA_DMAFATALERR  ((uint32_t)0x01U << 4U)

#define BM_FUSA_INT_STA_DMAEOBAERR  ((uint32_t)0x01U << 3U)

#define BM_FUSA_INT_STA_DMAEOBCERR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_INT_STA_SELFTESTMODEERR  ((uint32_t)0x01U << 1U)

#define BM_FUSA_INT_STA_REGPAREJENERR  ((uint32_t)0x01U << 0U)

#define FUSA_INT_STA_EN_OFF  0x1f4U

#define BM_FUSA_INT_STA_EN_DEBUGMODEERR  ((uint32_t)0x01U << 15U)

#define BM_FUSA_INT_STA_EN_PCTL1UNCORRERR  ((uint32_t)0x01U << 13U)

#define BM_FUSA_INT_STA_EN_PCTL0UNCORRERR  ((uint32_t)0x01U << 12U)

#define BM_FUSA_INT_STA_EN_PUSERUNCORRERR  ((uint32_t)0x01U << 11U)

#define BM_FUSA_INT_STA_EN_PADDRUNCORRERR  ((uint32_t)0x01U << 10U)

#define BM_FUSA_INT_STA_EN_PWDATAUNCORRERR  ((uint32_t)0x01U << 9U)

#define BM_FUSA_INT_STA_EN_PWDATACORRERR  ((uint32_t)0x01U << 8U)

#define BM_FUSA_INT_STA_EN_PWDATAFATALERR  ((uint32_t)0x01U << 7U)

#define BM_FUSA_INT_STA_EN_DMAUNCORRERR  ((uint32_t)0x01U << 6U)

#define BM_FUSA_INT_STA_EN_DMACORRERR  ((uint32_t)0x01U << 5U)

#define BM_FUSA_INT_STA_EN_DMAFATALERR  ((uint32_t)0x01U << 4U)

#define BM_FUSA_INT_STA_EN_DMAEOBAERR  ((uint32_t)0x01U << 3U)

#define BM_FUSA_INT_STA_EN_DMAEOBCERR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_INT_STA_EN_SELFTESTMODEERR  ((uint32_t)0x01U << 1U)

#define BM_FUSA_INT_STA_EN_REGPAREJENERR  ((uint32_t)0x01U << 0U)

#define FUSA_INT_EN_OFF  0x1f8U

#define BM_FUSA_INT_EN_DEBUGMODEERR  ((uint32_t)0x01U << 15U)

#define BM_FUSA_INT_EN_PCTL1UNCORRERR  ((uint32_t)0x01U << 13U)

#define BM_FUSA_INT_EN_PCTL0UNCORRERR  ((uint32_t)0x01U << 12U)

#define BM_FUSA_INT_EN_PUSERUNCORRERR  ((uint32_t)0x01U << 11U)

#define BM_FUSA_INT_EN_PADDRUNCORRERR  ((uint32_t)0x01U << 10U)

#define BM_FUSA_INT_EN_PWDATAUNCORRERR  ((uint32_t)0x01U << 9U)

#define BM_FUSA_INT_EN_PWDATACORRERR  ((uint32_t)0x01U << 8U)

#define BM_FUSA_INT_EN_PWDATAFATALERR  ((uint32_t)0x01U << 7U)

#define BM_FUSA_INT_EN_DMAUNCORRERR  ((uint32_t)0x01U << 6U)

#define BM_FUSA_INT_EN_DMACORRERR  ((uint32_t)0x01U << 5U)

#define BM_FUSA_INT_EN_DMAFATALERR  ((uint32_t)0x01U << 4U)

#define BM_FUSA_INT_EN_DMAEOBAERR  ((uint32_t)0x01U << 3U)

#define BM_FUSA_INT_EN_DMAEOBCERR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_INT_EN_SELFTESTMODEERR  ((uint32_t)0x01U << 1U)

#define BM_FUSA_INT_EN_REGPAREJENERR  ((uint32_t)0x01U << 0U)

#define CHN_NIB_FRAME1_OFF(n)  (0x200U + 24U*(n))

#define FM__CHN_FRAME1_CHN_NUM ((uint32_t)0xe0000000UL)
#define GFV_CHN_FRAME1_CHN_NUM(n) \
  (((n) & FM__CHN_FRAME1_CHN_NUM) >> 29UL)

#define FM_CHN_FRAME1_F ((uint32_t)0x10000000UL)
#define GFV_CHN_FRAME1_F(n) \
  (((n) & FM_CHN_FRAME1_F) >> 28UL)

#define FM_CHN_FRAME1_V ((uint32_t)0x8000000UL)
#define GFV_CHN_FRAME1_V(n) \
  (((n) & FM_CHN_FRAME1_V) >> 27UL)

#define FM__CHN_NIB_FRAME1_SCN ((uint32_t)0xf00UL)
#define GFV_CHN_NIB_FRAME1_SCN(n) \
  (((n) & FM__CHN_NIB_FRAME1_SCN) >> 8UL)

#define FM__CHN_NIB_FRAME1_CRC ((uint32_t)0x0fUL)
#define GFV_CHN_NIB_FRAME1_CRC(n) \
  (((n) & FM__CHN_NIB_FRAME1_CRC) >> 0UL)

#define FM_CHN_NIB_FRAME1_CHN_NIB_FRAME1  ((uint32_t)0xffffffffU << 0U)
#define FV_CHN_NIB_FRAME1_CHN_NIB_FRAME1(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_NIB_FRAME1_CHN_NIB_FRAME1)
#define GFV_CHN_NIB_FRAME1_CHN_NIB_FRAME1(v) \
  (((uint32_t)(v) & FM_CHN_NIB_FRAME1_CHN_NIB_FRAME1) >> 0U)

#define CHN_NIB_FRAME2_OFF(n)  (0x204U + 24U*(n))

#define FM_CHN_NIB_FRAME2_CHN_NIB_FRAME2  ((uint32_t)0xffffffffU << 0U)
#define FV_CHN_NIB_FRAME2_CHN_NIB_FRAME2(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_NIB_FRAME2_CHN_NIB_FRAME2)
#define GFV_CHN_NIB_FRAME2_CHN_NIB_FRAME2(v) \
  (((uint32_t)(v) & FM_CHN_NIB_FRAME2_CHN_NIB_FRAME2) >> 0U)

#define CHN_NIB_STAMP_OFF(n)  (0x208U + 24U*(n))

#define FM_CHN_NIB_STAMP_CHN_NIB_STAMP  ((uint32_t)0xffffffffU << 0U)
#define FV_CHN_NIB_STAMP_CHN_NIB_STAMP(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_NIB_STAMP_CHN_NIB_STAMP)
#define GFV_CHN_NIB_STAMP_CHN_NIB_STAMP(v) \
  (((uint32_t)(v) & FM_CHN_NIB_STAMP_CHN_NIB_STAMP) >> 0U)

#define CHN_SER_FRAME1_OFF(n)  (0x20cU + 24U*(n))

#define FM_CHN_SER_FRAME2_C (0x80000000UL)
#define GFV_CHN_SER_FRAME2_C(v) \
  (((v) & FM_CHN_SER_FRAME2_C) >> 31UL)

#define FM_CHN_SER_FRAME2_T (0x40000000UL)
#define GFV_CHN_SER_FRAME2_T(v) \
  (((v) & FM_CHN_SER_FRAME2_T) >> 30UL)

#define FM_CHN_SER_FRAME2_CRC (0x3f000000UL)
#define GFV_CHN_SER_FRAME2_CRC(v) \
  (((v) & FM_CHN_SER_FRAME2_CRC) >> 24UL)

#define FM_CHN_SER_FRAME2_MID (0xff0000UL)
#define GFV_CHN_SER_FRAME2_MID(v) \
  (((v) & FM_CHN_SER_FRAME2_MID) >> 16UL)

#define FM_CHN_SER_FRAME2_DATA (0xffffUL)
#define GFV_CHN_SER_FRAME2_DATA(v) \
  (((v) & FM_CHN_SER_FRAME2_DATA) >> 0UL)

#define FM_CHN_SER_FRAME1_CHN_SER_FRAME1  ((uint32_t)0xffffffffU << 0U)
#define FV_CHN_SER_FRAME1_CHN_SER_FRAME1(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_SER_FRAME1_CHN_SER_FRAME1)
#define GFV_CHN_SER_FRAME1_CHN_SER_FRAME1(v) \
  (((uint32_t)(v) & FM_CHN_SER_FRAME1_CHN_SER_FRAME1) >> 0U)

#define CHN_SER_FRAME2_OFF(n)  (0x210U + 24U*(n))

#define FM_CHN_SER_FRAME2_CHN_SER_FRAME2  ((uint32_t)0xffffffffU << 0U)
#define FV_CHN_SER_FRAME2_CHN_SER_FRAME2(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_SER_FRAME2_CHN_SER_FRAME2)
#define GFV_CHN_SER_FRAME2_CHN_SER_FRAME2(v) \
  (((uint32_t)(v) & FM_CHN_SER_FRAME2_CHN_SER_FRAME2) >> 0U)

#define CHN_SER_STAMP_OFF(n)  (0x214U + 24U*(n))

#define FM_CHN_SER_STAMP_CHN_SER_STAMP  ((uint32_t)0xffffffffU << 0U)
#define FV_CHN_SER_STAMP_CHN_SER_STAMP(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_SER_STAMP_CHN_SER_STAMP)
#define GFV_CHN_SER_STAMP_CHN_SER_STAMP(v) \
  (((uint32_t)(v) & FM_CHN_SER_STAMP_CHN_SER_STAMP) >> 0U)

#define DMA_FRAME1_OFF  0x300U

#define FM_DMA_FRAME1_DMA_FRAME1  ((uint32_t)0xffffffffU << 0U)
#define FV_DMA_FRAME1_DMA_FRAME1(v) \
  (((uint32_t)(v) << 0U) & FM_DMA_FRAME1_DMA_FRAME1)
#define GFV_DMA_FRAME1_DMA_FRAME1(v) \
  (((uint32_t)(v) & FM_DMA_FRAME1_DMA_FRAME1) >> 0U)

#define DMA_FRAME2_OFF  0x304U

#define FM_DMA_FRAME2_DMA_FRAME2  ((uint32_t)0xffffffffU << 0U)
#define FV_DMA_FRAME2_DMA_FRAME2(v) \
  (((uint32_t)(v) << 0U) & FM_DMA_FRAME2_DMA_FRAME2)
#define GFV_DMA_FRAME2_DMA_FRAME2(v) \
  (((uint32_t)(v) & FM_DMA_FRAME2_DMA_FRAME2) >> 0U)

#define DMA_STAMP_OFF  0x308U

#define FM_DMA_STAMP_DMA_STAMP  ((uint32_t)0xffffffffU << 0U)
#define FV_DMA_STAMP_DMA_STAMP(v) \
  (((uint32_t)(v) << 0U) & FM_DMA_STAMP_DMA_STAMP)
#define GFV_DMA_STAMP_DMA_STAMP(v) \
  (((uint32_t)(v) & FM_DMA_STAMP_DMA_STAMP) >> 0U)

#define CHANNEL_TICK_RESULT_OFF(n)  (0x340U + 4U*(n))

#define FM_CHANNEL_TICK_RESULT_TICK_RESULT  ((uint32_t)0x3fffU << 0U)
#define FV_CHANNEL_TICK_RESULT_TICK_RESULT(v) \
  (((uint32_t)(v) << 0U) & FM_CHANNEL_TICK_RESULT_TICK_RESULT)
#define GFV_CHANNEL_TICK_RESULT_TICK_RESULT(v) \
  (((uint32_t)(v) & FM_CHANNEL_TICK_RESULT_TICK_RESULT) >> 0U)

#define CHN_DEBUG_OFF(n)  (0x380U + 4U*(n))

#define BM_CHN_DEBUG_EN  ((uint32_t)0x01U << 31U)

#define FM_CHN_DEBUG_BUS  ((uint32_t)0x3fffffffU << 0U)
#define FV_CHN_DEBUG_BUS(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_DEBUG_BUS)
#define GFV_CHN_DEBUG_BUS(v) \
  (((uint32_t)(v) & FM_CHN_DEBUG_BUS) >> 0U)

#define CHN_SPC_CTRL_OFF(n)  (0x400U + 4U*(n))

#define BM_CHN_SPC_CTRL_SPC_EN  ((uint32_t)0x01U << 31U)

#define BM_CHN_SPC_CTRL_SPC_LOOP4  ((uint32_t)0x01U << 30U)

#define BM_CHN_SPC_CTRL_TRIG_MODE  ((uint32_t)0x01U << 18U)

#define BM_CHN_SPC_CTRL_TICK_BASE  ((uint32_t)0x01U << 17U)

#define FM_CHN_SPC_CTRL_EXT_TRIG_SEL  ((uint32_t)0x7U << 14U)
#define FV_CHN_SPC_CTRL_EXT_TRIG_SEL(v) \
  (((uint32_t)(v) << 14U) & FM_CHN_SPC_CTRL_EXT_TRIG_SEL)
#define GFV_CHN_SPC_CTRL_EXT_TRIG_SEL(v) \
  (((uint32_t)(v) & FM_CHN_SPC_CTRL_EXT_TRIG_SEL) >> 14U)

#define FM_CHN_SPC_CTRL_TRIG_DEL  ((uint32_t)0x7fU << 7U)
#define FV_CHN_SPC_CTRL_TRIG_DEL(v) \
  (((uint32_t)(v) << 7U) & FM_CHN_SPC_CTRL_TRIG_DEL)
#define GFV_CHN_SPC_CTRL_TRIG_DEL(v) \
  (((uint32_t)(v) & FM_CHN_SPC_CTRL_TRIG_DEL) >> 7U)

#define FM_CHN_SPC_CTRL_PULSE_LEN  ((uint32_t)0x7fU << 0U)
#define FV_CHN_SPC_CTRL_PULSE_LEN(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_SPC_CTRL_PULSE_LEN)
#define GFV_CHN_SPC_CTRL_PULSE_LEN(v) \
  (((uint32_t)(v) & FM_CHN_SPC_CTRL_PULSE_LEN) >> 0U)

#define CHN_SPC_LPSTEP_OFF(n)  (0x420U + 4U*(n))

#define FM_CHN_SPC_LPSTEP_LPMASK  ((uint32_t)0xfU << 28U)
#define FV_CHN_SPC_LPSTEP_LPMASK(v) \
  (((uint32_t)(v) << 28U) & FM_CHN_SPC_LPSTEP_LPMASK)
#define GFV_CHN_SPC_LPSTEP_LPMASK(v) \
  (((uint32_t)(v) & FM_CHN_SPC_LPSTEP_LPMASK) >> 28U)

#define FM_CHN_SPC_LPSTEP_LPSTEP3  ((uint32_t)0x7fU << 14U)
#define FV_CHN_SPC_LPSTEP_LPSTEP3(v) \
  (((uint32_t)(v) << 14U) & FM_CHN_SPC_LPSTEP_LPSTEP3)
#define GFV_CHN_SPC_LPSTEP_LPSTEP3(v) \
  (((uint32_t)(v) & FM_CHN_SPC_LPSTEP_LPSTEP3) >> 14U)

#define FM_CHN_SPC_LPSTEP_LPSTEP2  ((uint32_t)0x7fU << 7U)
#define FV_CHN_SPC_LPSTEP_LPSTEP2(v) \
  (((uint32_t)(v) << 7U) & FM_CHN_SPC_LPSTEP_LPSTEP2)
#define GFV_CHN_SPC_LPSTEP_LPSTEP2(v) \
  (((uint32_t)(v) & FM_CHN_SPC_LPSTEP_LPSTEP2) >> 7U)

#define FM_CHN_SPC_LPSTEP_LPSTEP1  ((uint32_t)0x7fU << 0U)
#define FV_CHN_SPC_LPSTEP_LPSTEP1(v) \
  (((uint32_t)(v) << 0U) & FM_CHN_SPC_LPSTEP_LPSTEP1)
#define GFV_CHN_SPC_LPSTEP_LPSTEP1(v) \
  (((uint32_t)(v) & FM_CHN_SPC_LPSTEP_LPSTEP1) >> 0U)

#define CHN_SPC_UPD_OFF(n)  (0x440U + 4U*(n))

#define BM_CHN_SPC_UPD_BIT  ((uint32_t)0x01U << 0U)

#define CHN_SPC_SW_TRIG_OFF(n)  (0x460U + 4U*(n))

#define BM_CHN_SPC_SW_TRIG_BIT  ((uint32_t)0x01U << 0U)

#endif /* SENT_REG_H */
/* End of file */
